The present invention relates to an improvement in a logic circuit; and more particularly, it relates to a logic circuit which can easily perform its own functional test.
Generally, when an integrated circuit and the like is first installed, the functional test of the integrated circuit and the like is performed. For example, the functional test of a logic circuit 1 (as shown in FIG. 1) is ordinarily performed as follows. First, test pattern signals are input to a plurality of input terminals 3 of the logic circuit 1. Next, output signals are output from a plurality of output terminals 5 and compared with expected values which have been preliminarily prepared. When the output signals and expected values coincide, logic circuit 1 is deemed to be operating correctly. Conversely, when the output signals are expected values do not coincide, it is determined that the logic circuit 1 is malfunctioning.
The object of a functional test is to check whether or not a logic circuit works as is expected. The smaller the number of input test patterns which are required to check for all possible defects in the components of the logic circuit, the more efficient the functional test. The number of input test patterns required depends on the number of components which make up the logic circuit and their complexity. An increase in the number of output terminals, however, results in a decrease in the number of required input test patterns because defects in the logic components can be more easily detected.
Sequential circuits represents one class of logic circuits. Another class is combinational circuits, which, compared with sequential circuits, do not contain memory. A common method of testing sequential circuits is the scan-path method. FIG. 2 shows one of the logic circuits which may be used to implement the scan-path method. This circuit (FIG. 2) is a modification of the logic circuit shown in FIG. 7 of U.S. Pat. No. 3,783,254. Generally, a sequential circuit can be expressed as a combination of registers 11-1 to 11-n and a combinational circuit 13. The sequential circuit of FIG. 2 further comprises changeover switches 15-1 to 15-n. FIG. 3 shows one of these switches, e.g., the switch 15-1. As shown in the figure, a switch signal SW is supplied to the first input terminal of a 2-input AND gate 21. This signal SW is supplied via an inverter 23 to the first input terminal of a 2-input AND gate 25. A scan input signal IN is supplied to the second input terminal of the AND gate 21. The second input terminal of the AND gate 25 is connected to the combinational circuit 13. The output terminals of the AND gates 21 and 25 are coupled to the first and second input terminals of a 2-input OR gate 27, the output terminal of which is coupled to the register 11-1.
Since the other changeover switches 15-2 to 15-n have the same structure as the switch 15-1, the registers 11-1 to 11-n store the data provided by the combinational circuit 13 as long as the switch signal SW is at a low level. On the other hand, the registers 11-1 to 11-n operate as a shift register when the switch signal SW is at a high level. The scan-path method is performed as follows. Test pattern signals are input to a plurality of input terminals 17 of the combinational circuit 13. Output signals from output terminals 19 are compared with expected values which have already been prepared. The switch signal SW is switched so that the registers 11-1 to 11-n act as shift registers. A pulse signal .phi. is input to the registers 11-1 to 11-n to shift the contents of the registers. The contents of the respective registers 11-1 to 11-n are sequentially fetched at the output of register 11-n, and compared with the expected values.
In the case of the scan-path method, registers play a further role as additional output terminals. Since the operation of the combinational circuit becomes more easy to observe, the number of required test patterns which are input to the input terminals 17 can be reduced.
According to the ordinary method for the functional test, the number of required test patterns increases as logic circuit 1 becomes more complicated. It raises a problem in that it requires a long time to perform the full functional test.
On the other hand, according to the scan-path method, the number of required test patterns can be reduced by using registers as output terminals. However, in the scan-path method, observable nodes inside a logic circuit are limited by the number of registers 11-1 to 11-n. As a result, when an increase in the number of observable logic nodes is desired, it is necessary to add registers to the logic circuit. A register has a larger number of constituent elements than an ordinary gate circuit. Thus, this method has a drawback in that the size of the whole circuit becomes large. Further, an increase of the number of registers 11-1 to 11-n increases the time needed to retrieve the contents of those registers and perform the functional test.
With the recent high intergration and high density of semiconductor devices, the functional test is becoming more and more important. At the same time, there is a problem in that it takes a longer time to perform a functional test on such density integration devices.